The present invention relates generally to the field of adders and multipliers. Previously, high-frequency multipliers have used bipolar transistors. However, the precision of the product is limited by the matching of the transistors and in particular by the precision of the emitter-base junctions which are very sensitive to temperature variations. This problem is compounded by the fact that bipolar transistors dissipate substantial power which is a prime factor in the increase of junction temperature. In order to alleviate the problem of transistor matching, the more recent solutions have used the "integration" approach, i.e., the fabrication of a full multiplication function within a single substrate of silicon. However, due to the parasitic capacitances inherent to the latter technique, the high-frequency properties of bipolar transistors were drastically degraded.
Other attempts to provide suitable multipliers have involved the use of MOSFETS. These also have been unsuccessful due to the low frequency response of the whole multiplier which is typically below 100 KHz.
Presently, the implementation of the multiplication function is achieved by hybrid techniques with the use of accurately matched discrete devices provided in a 2" .times. 1" .times. 1/2" package. These devices, however, have the serious disadvantage of appreciable power dissipation.